This invention relates generally to semiconductor integrated circuit packages and more particularly, it relates to an improved method for fabricating a chip size package which can accommodate high or low pin-count dies with a minimum amount of substrate real estate being required.
In recent years, there has been an increased interest in the packaging industry in an area generally known as a die size solution. The reason for the search for new alternatives is that the package and interconnection industry has moved away from the use of pins as connectors for electronic packaging due to the high cost of fabrication, the high failure rate in the connections, and the limitation on the density of input/output pins. Consequently, there exists a need to eliminate the classic package performance problems and to reduce the size, weight, and cost of standard packages. As a result, there has been developed new die size packaging alternatives which are classified into three main groups: (1) Bare die or Known Good Die (KGD), (2) flip chip, and (3) chip size package (CSP).
With respect to the chip size package (CSP) alternative, the package typically occupies in the range of 1 to 1.2 times the area of the chip in the package. The primary advantage of the CSP is that they can accept a die design with peripheral bond pads and route the signal to a ball on the surface to make it suitable for surface mounting. The rerouting approach on the surface of the die reduces the handling and mounting issues over the other two mentioned alternatives and facilitates in the testing processes of the product. However, the conventional versions of the CSP alternatives generally use a wire bond technique to connect the bond pads to an interposer surface for holding the solder balls, thereby introducing increased electrical resistance and conductance.
It would therefore be desirable to provide an improved method for fabricating a chip size package which is relatively simple in construction and easy to assemble. It would be also expedient to provide a chip size package which eliminates the need for TAB (tape-automated bonding) or wire bonding in order to reduce electrical resistance and conductance.